The present invention generally relates to complimentary metal-oxide semiconductors (CMOS) and metal-oxide-semiconductor field-effect transistors (MOSFET), and more specifically, to nanowire device fabrication.
The MOSFET is a transistor used for switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or high dielectric constant (high-k) dielectrics, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
N-type field effect transistors (nFET) and p-type field effect transistors (pFET) are two types of complementary MOSFETs. The nFET includes n-doped source and drain junctions and uses electrons as the current carriers. The pFET includes p-doped source and drain junctions and uses holes as the current carriers.
Nanowire devices are gate-all-around devices that include channel regions formed from semiconductor nanowires. The gate stacks conform around the nanowires to form a gate-all-around device. The nanowire devices are often formed using a fabrication process that uses nanosheets to form nanosheet fins. The nanosheet fins can be formed into nanowires in the channel regions of the devices.